The present invention relates to an optical information control device for recording information on an optical disk and replaying information recorded on an optical disk.
First of all, a prior optical information control device is explained.
FIG. 14 is a block diagram of a prior optical information control device.
In FIG. 14, 1 is an optical disk.
2 is an optical head.
3 is a head amp.
4 is a waveform shaping circuit.
5 is a laser driver circuit.
6 is a decoder.
7 is an encoder.
8 is a format control section.
9 is a buffer.
10 is an error correction circuit.
11 is a SCSI control section.
12 is an internal bus.
13 is a SCSI bus.
14 is the host computer.
15 is an actuator.
16 is a servo-circuit.
17 is a PLL (Phased Locked Loop).
18 is an error detection circuit.
19 is a mark detection circuit.
20 is a lock signal that is a completion signal of PLL synchronization.
21 is a clock (rdclk) synchronized to optical disk data.
211 is a crystal oscillator.
22 is a clock (rfclk) output from the crystal oscillator 211.
23 is an address mark detection signal.
24 is a sector mark detection signal.
52 is an output enable circuit for making an output from the mark detection circuit 19 enabled.
213 is a selector for switching over the rdclk 21 and the rfclk 22 by the lock signal 20.
57 is an output (chclk) from the selector 213.
208 is a 16-frequency divider that outputs a byte clock BCLK.
203 is a counter.
201 and 210 are registers for holding values loaded into the counter 203.
202 and 209 are registers for holding values to become the object of comparison to output from the counter 203.
204 and 207 are zero detector circuits.
205 is a comparison circuit.
206 is a counter.
212 is a logical sum.
214 is a window signal.
215 is a selector that selects values to be loaded into the counter 203.
216 is a selector for selecting values to become the object of comparison to the counter 203.
217 is a window central signal.
218 is an RS flip-flop.
Next, operation of an optical information control device configured by above components is explained.
First, the sector format of an optical disk is explained.
FIG. 4 shows the sector format of an optical disk.
In this figure, SM is a 5-byte sector mark indicating beginning location of the sector.
VFO is a Variable Frequency Oscillator, where VFO1 is of 12-byte, VFO2 is of 8-byte, VFO3 is of 12-byte.
AM is an address mark. There are three AM's in a sector.
Each of ID1-ID3 is a 5-byte identification code, configured by a two-byte truck number, a 1-byte sector number, and a 2-byte error detection code CRC.
PA is a postamble of 1-byte.
ODF is an off-set detection flag that is an offset correction mirror surface for servo.
GAP is a gap, each gap is of 3-byte.
FLAG is a 5-byte flag.
ALPC is a 2-byte, used for a laser power test, etc.
SYNC is a 3-byte synchronous code.
DATA is a data area including CRC and ECC.
A sector comprises the sector mark SM, VFO1, VFO2, VFO3, three address mark AM's, identification codes ID1-ID3, a postamble PA, off-set detection flag ODF, two gaps GAPs, flag FLGs, ALPC, a synchronous code SYNC and a data area DATA.
In addition, one byte of these marks, data, etc. consists of 16 01 pits. For example, the pit pattern of address mark AM is 0100100000000100.
In FIG. 14, operation of the servo system of the optical disk having such sector format.
A laser beam output from the optical head 2 is reflected by the optical disk 1.
This reflected beam is transmitted to the error detection circuit 18 via the head amp 3.
The error detection circuit 18 detects slippage between the optical head 2 and a track on the optical disk 1 using the reflected beam.
The servo circuit 16 generates a control signal for the actuator 15 based on the detected slippage and determines location of the optical head 2 by controlling the actuator 15.
Next, by read operation of the optical disk drive, data on the optical disk 1 is read in via the optical head 2 and the head amp 3.
The waveform of the data read in is shaped at the waveform shaping circuit 4, and the data is transferred to the decoder 6.
The output of decoder 6 is transferred to the format control section 8.
The format control section 8 reads ID1-ID3 that were decoded at the decoder 6 and detects a sector indicating beginning of data processing.
When the objective sector is detected, the read data processing of the target sector's data begins.
The data is processed error check an error correction at the error correction circuit 10 and is transferred to the buffer 9.
Then this data is transferred to the host computer 14 by the SCSI control section via the SCSI bus 13.
At this time, at the format control section 8, reading of ID1-ID3 is conducted by the address mark detection signal 23 as a trigger, which is a detection signal for the address mark AM located before ID1-ID3.
The re-setting of the decoder 6 is also triggered by the address mark detector signal 23.
The rdclk 21, a synchronous signal generated at the PLL 17 on the basis of patterns of VFO1-VFO3 output from the waveform shaping circuit 4 is used as the decoder read clock.
Moreover, there is a method as described in Japanese Patent Laid-Open No. 251371 (1989) of generating a read clock by inputting an intensity signal for tracking-servo from an optical head.
Next, how to detect the address mark AM is explained in detail.
Detection of the address mark AM is conducted by pattern matching, etc. in the mark detection circuit 19.
However, because pattern length of the address mark AM is only 1 byte, sometimes patterns from areas other than the address mark AM are mistakenly detected.
Therefore, the window signal 214, which enables detection of mark signals only for a certain period, is used to generate the address mark detection signal 23.
Following is an explanation of the generation of window signal 214 and address mark detection signal 23, in accordance with FIG. 14 and 15.
Where, the first window signal 214 that is generated has a window width of .+-.2 bytes and that of the second signal is .+-.1 byte.
For this reason, the registers 202 and 209 are set to "2" and "1" respectively.
The counters 203 and 206 are used to generate the window signal 214. These counters are operated by the byte clock BCLK.
The byte clock BCLK is generated by dividing the chclk 57 to 16-division at the 16-frequency divider 208. Basically, it is synchronized with each data byte.
When synchronization at PLL is established, the chclk 57 is the clock rdclk 21, which is in synchronization with the pits of data (16 pits =1 byte). When synchronization is not established, it becomes the clock rfclk 22 output from the crystal oscillator 211.
Using the patterns output from the waveform shaping circuit 4, the sector mark detection circuit 19 comprising pattern matching circuits, etc. detects the sector mark SM and output the sector mark detection signal 24.
Using the sector mark detection signal 24, the selector 215 selects the register 201.
The counter 203 loads the value (=12) stored in the resistor 201 starts down-counting by the byte clock BCLK as shown in FIG. 15.
At this time, the selector 216 selects the register 202 and outputs "2".
The set signal (A) is output by the comparison circuit 205 when the value from the counter 203 is smaller 1 than output (=2) from the selector 216, that is, when the value of the counter 203 becomes 1.
Then, the window signal 214 becomes active at a rising edge of the set signal (A).
On the other hand, when an output of the counter 203 becomes "0", the output "2" of the selector 216 is loaded into the counter 206 and the counter 206 downcounts.
And, when the value of counter 206 becomes "0," the reset signal (B) is generated.
At a rising edge of the reset signal (B), the window signal 214 becomes inactive.
When output of the counter 203 becomes "0," the window central signal 217 is generated.
During the period when the window signal 214 is active, the window central signal 217 is used in place of the mark detection signal when the address mark AM was not detected.
During the period when the window signal 214 is active, the address mark detection signal 23 is output from the output enable circuit 52 when the address mark AM is detected.
In the generation of the second window signal, the value (=13) stored in the register 210 is loaded into the counter 203 by the address mark detection signal 23 and the counter 203 down-counts.
Then the register 209 is selected and, because "1" is output from the selector 216 when the value of counter 203 becomes "0" the set signal (A) and the central window signal 217 are output.
Also, "1" is loaded into the counter 206, and when the value of counter 206 becomes "0", the reset signal (B) is output.
Then, the window signal 214 is created by the set signal (A) and the reset signal (B).
With the above-mentioned prior optical information control device, when synchronization of 01 bit data read out from the disk and rdclk read clock is lost, synchronization of the byte clock BCLK and the byte data is lost.
Therefore, the center of the window signal slips in pit units in relation to actual AM position.
Once a window signal slips out of synchronization, this slippage is propagated. This influences window signal detection of the next address mark.
When the slippage becomes great, the address mark AM ceases to exist at locations at which window signals become active, and the address mark detection signals stop being output.
Location slippage of the window central signal becomes a great problem when the window central signal is used in place of a mark detection signal as a reset signal for decoder or a trigger signal for ID reading.
Also, there is an art to solve this problem as described in Japanese Patent Laid-Open No. 157874 (1991). However, this is not a complete solution because it can not correct the phase of read clock.
Furthermore, in the above-mentioned example of a prior optical information control device, the window location or window width setting cannot be determined using pit units. It is possible to temporarily activate the counter by the clock synchronized to the pit data instead of byte clock BCLK and set a pit units value to register, but the value of the data being used would then be increased 16-fold.
Therefore, the register bit width, the counter bit width and the width of the signal line transmitting these output signals increases 4-fold, so the hardware increases.